ASIC/FPGA Design Engineer
VLSI design engineer that will join Ceragon Digital Solution group will be:
Taking part in the architecture and implementation of complex: Wireless Networking IPs Packet processing Working closely with Ceragon design team developing together the next generation ASIC/FPGA Working closely with Ceragon verification team.
The ideal candidate has the following:
BSc in Computer science/ Electrical engineering At least 3-5 years of experience as VLSI Design Engineer with Verilog Background in Networking IPs and SOC architecture (Ethernet, networking processor, CPU etc)
Strong background in Networking Strong background in IP protocols Experience with synthesis and STA and SDC (Static Timing Analysis. Experienced in implementation of complex communication IP. (CPU/DSP/Mctrl) Understanding of fix point implementation, modulation, coding, detection, equalization, timing/phase recovery.
Verilog VHDL, Code Linter, CDC (Cross Domain Clocking), SDC (Synthesis Design Constraint), Altera/Xilinx, Synthesis, STA (Static Timing Analysis), Specman Verification.
We are looking for candidates capable of self-learning and working in a dynamic environment, with excellent communication skills and team player, capable of grasping an overall view of complex systems.