VLSI design manager will join Ceragon’s Design group.
He will manage a VLSI/ASIC team that includes few engineers in IL and few oversea.
The manager will be taking part in architecture and micro-architecture, design, IP integration and other tasks as part of the chip development processes.
BSc in Computer science/ Electrical engineering from known University – Must.
8+ years of experience in VLSI design – Must.
At least 3 years of experience as team leader or team manager – Must.
Deep knowledge in Verilog – Must.
Experience in micro-architecture and design of complex blocks – Must.
Familiar with the verification process of a block (test plan, coverage, etc.) – Must.
Excellent communication skills in English (written and verbal) – Must.
Experience with multi-clock domain designs – Advantage.
Script knowledge (TCL, Perl, etc.) – Advantage.
Experience with chip frontend process (synthesis/STA) – Advantage.
Strong execution orientation.
Thorough and accurate.
Good communicator and team player.
Fast leaning skills.